IDT5V49EE904NLGI8【PDF 2/29 页】IC PLL CLK GEN 200MHZ 32VFQFN

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IDT5V49EE904

EEPROM PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

IDT EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE904

REV P 092412

Spread Spectrum Generation (PLL3)

PLL3 support spread spectrum generation capability, which

users have the option of turning on and off. Spread

spectrum profile, frequency, and spread are fully

programmable (within limits). The technique is different from

that used in PLL0. The programmable spread spectrum

generation parameters are SS_D3[7:0], SSVCO[15:0],

SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the

memory address range of 0x4C to 0x85 for PLL3. The

spread spectrum generation on PLL3 can be

enabled/disabled using the SSENB bit. To enable spread

spectrum, set SSENB = '1'.

For Spread Enabled:

Spread spectrum is configured using SS_D3(spread

spectrum reference divide)

and SSVCO (spread spectrum loop feedback counter).

SS is the total Spread Spectrum amount (I.e. center spread

+0.5% has a total spread of 1.0% and down spread -0.5%

has a total spread of 0.5%.)

Loop Filter

The loop filter for each PLL can be programmed to optimize

the jitter performance. The low-pass frequency response of

the PLL is the mechanism that dictates the jitter transfer

characteristics. The loop bandwidth can be extracted from

the jitter transfer. A narrow loop bandwidth is good for jitter

attenuation while a wide loop bandwidth is best for low-jitter

frequency generation. The specific loop filter components

that can be programmed are the resistor via the RZ[3:0] bits,

zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and

the charge pump current via the IP[2:0] bits (for PLL0, PLL1

and PLL2) or IP[3:0] (for PLL3).

The following equations govern how the loop filter is set for

PLL0 - PLL2:

Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0

kOhm

Zero capacitor (Cz) = 196 pF + CZ* 217 pF

Pole capacitor (Cp) = 15 pF

Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA

VCO gain (KVCO) = 900 MHz/V * 2

The following equations govern how the loop filter is set for

PLL3:

For Non-Spread Spectrum Operation:

For Spread Spectrum Operation:

Zero capacitor (Cz) = 250 pF

Pole capacitor (Cp) = 15 pF

For Non-Spread Spectrum Operation:

For Spread Spectrum Operation:

VCO gain (KVCO) = 900 MHz/V * 2

SS_D3

(Eq. 10)

4 * F

MOD

SSVCO =

VCO

MOD

[0.5 *

(Eq. 11)

( 1 + SS/400) + 5]

Resistor(Rz)=

(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))

* RZ[0] + 6*(1 – RZ[0])

kOhms (Eq. 12)

Resistor(Rz)=

(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))

* RZ[0] + 6*(1 – RZ[0])

kOhms (Eq. 13)

Charge

pump(Ip)

24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))

A (Eq. 14)

3+(5* IP[3]) +(11* IP[4])

Charge

pump(Ip)

12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))

A (Eq. 14)

27+(5* IP[3]) +(11* IP[4])

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